A multi-core-based heterogeneous parallel turbo decoder

نویسندگان
چکیده

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

A multi-core-based heterogeneous parallel turbo decoder

It has always been a challenging task to implement a turbo decoder because it’s typically the most compute-intensive and time-consuming part in a wireless communication system. This becomes especially obvious when realizing a turbo decoder through CPUs or GPUs. In this paper, we present a heterogeneous and highly reconfigurable parallel turbo decoder for LTE by employing a multi-core processor ...

متن کامل

Analog Sliding Window Decoder Core for Mixed Signal Turbo Decoder

The application of turbo codes in modern communication systems makes decoding a time and power consuming task. It is known that analog decoder are superior to digital decoder designs in terms of speed and power consumption. The fact that a modification of a single code parameter like the block length requires a new analog decoder implementation, in combination with a complexity, which grows lin...

متن کامل

Parallel VLSI architecture for MAP turbo decoder

Turbo codes achieve performance near the Shannon limit. Standard sequential VLSI implementation of turbo decoding requires many iterations and incurs a long latency, which cannot be tolerated in some applications. A novel parallel VLSI architecture for turbo decoding is described, comprising multiple SISO elements, operating jointly on one turbo coded block, and a new parallel interleaver. Late...

متن کامل

A novel QPP interleaver for parallel turbo decoder

Quadratic permutation polynomial (QPP) interleaver is more suitable for parallel turbo decoding due to it is contention-free. However, the parallel address generation of QPP is area-consuming when the parallel degree P is large, and the data shuffle between memory banks and processing elements (PE) introduces large interconnect cost. This paper first evaluates the area and power cost of three t...

متن کامل

Implementation of a parallel turbo decoder with dividable interleaver

In this paper, VLSI architecture for an efficient turbo decoder with parallel architecture has been studied to achieve high-throughput. For 100% PE utilization, a dividable interleaving method is proposed, which not only solves the memory conflict problem in extrinsic information memory, but also reduces the required memory for interleaver. We mapped the proposing parallel turbo decoder with 4 ...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

ژورنال

عنوان ژورنال: IEICE Electronics Express

سال: 2017

ISSN: 1349-2543

DOI: 10.1587/elex.14.20170768